bflyw d0,d1,d2 ;result in d2 & d3 ; result d2 = 45050204 ; d2 = d1 + d0 ; result d3 = 42ff0102 ; d3 = d1 - d0 ; d2 can be changed to any EVEN data-register
; logic operation move.b #%11100010,d3 ; result d3 = 000000e2 ; this would be d1 as mask selecting d0, otherwise d2
minterm d0-d3,d4 ; result d4 = 11100010
; powerfull logic operation! ; any locical bit function can be made in d4 for ; the 3 64_bit inputs.
; Other logic_op, set bit if only 1 of the 3 inputs is set move.b #%00010110,d3 ; result d3 = 00000016
minterm d0-d3,d6 ; result d6 =00010110 move.l d6,d5
; same logic, new inputs: move.l #$01234567,d0 move.l #$11002266,d1 move.l #$f0f000ff,d2
minterm d0-d3,d6 ; result d6 =e0d36798
; note: ; source is 4 following data-registers, where the first one is modulo 4 ; destination is EVEN data-register.
Tommo Noorduin
Posts 136 23 Apr 2022 19:04
; a tool
; The last value written to chip-registers can be read. ; by using dfe000
move.l $dfe080,a0 ;copper list 1 pointer, a0 =000055b8 move.l $dfe084,a1 ;copper list 2 pointer, a1 =00005630
move.w $dff002,d0 ;dma con read, dmacon = 03f0 move.w $dfe002,d1 ;d1 = 0000: last value written to this read-only address ; is zero because there has been no writting to that location.
move.w $dfe096,d2 ;dma con, d2 = 8180 ; so the last action was: set bitplane & copper
transhi d0-d3,d4:d5 ; result d4 = (112299aa)12341111 ; result d5 = (3344bbcc)56781111
translo d0-d3,d6:d7 ; result d6 = (5566ddee)9abc1111 ; result d7 = (7788ff00)def01111
illegal
; A bit like c2p ; C2P does transpose 8x8 bits ; TRANS does transpose 4x4 words
; Same restrictions as minterm: ; source is 4 following data-registers, where the first one is modulo 4 ; destination pair, the first must be EVEN data-register.
Tommo Noorduin
Posts 136 25 Apr 2022 14:44
; 4 x word multiply in 3 variations ; hi part, low part & middle part
Isn't the mask read from the contents of Dn? It would justify this
storem3 d0,d0,(a0)+ ; result val0 = 000000009abcdef0
because in the documentation it says
d[0] = ( m & (1<<(7-i)) ) ? a[0] : d[0];
Since bit 7 is 1, you get the 0xf0 as the lowest byte in val0. Mask 0xf0 means that you'll get the lower 4 bytes from d0 and the rest from val0. Mask 0x0f would be the opposite i.e. 1234567800000000.
The other results (for d1,d2,d3,d4,etc.) really depend on the value stored at each register.
Please also note that the Mask field in extension word 1 (bits 8-11) and the corresponding extension bit in word 0 (bit 6) would not be enough to filter the 8 possible bytes in a qword. So it makes sense that the mask is obtained from a data register.
At least this is how I interpret the little information/documentation that we have available.
Cheers aorlando
Tommo Noorduin
Posts 136 28 Apr 2022 17:45
more STOREM3
Hi António,
Before your post i was aware storem3 is more complex. I was thinking something like:
Store bytes from source to destination, depending on mode 0: 2x 32bit color when msb=1 1: 2x 32bit color when msb=1 (but only when individual R,G,B>0) 2: src 3: 4x 15bit color when msb=0
But i am in the dark here. I am trying to gain knowledge of the new 68080 stuff, just like you.
António Orlando wrote:
At least this is how I interpret the little information/documentation that we have available.
That is why my guessing on storem3. looking at how it behaves.
d[0] = ( m & (1<<(7-i)) ) ? a[0] : d[0]; is probably for storem only.
If you have/see documentation of storem3 i would apreciate that! Well actually anything about special 68080 instructions is good. Just post links here!
I hope to contribute a bit by showing some examples.
The snippets are for everyone to see what it does. They can copy it and use it in the debugger from devpac, so they can even do the steps themself to see what it does inside the CPU.
Thank you for you post, nice to know you are also looking at the powerfull possibilities the 68080 has.
Gunnar von Boehn (Apollo Team Member) Posts 6254 29 Apr 2022 06:37
Tommo Noorduin wrote:
If you have/see documentation of storem3 i would apreciate that!
Store3M does write 8 Byte in 1 instruction. The write enables are depending on content of the data. This means only non transparent pixels are written. This makes STORE3M optimal for Soft Sprites.
STORE3M supports 8bit, 16bit, 15bit, and 32bit pixels
Tommo Noorduin
Posts 136 29 Apr 2022 08:45
Gunnar wrote:
STORE3M supports 8bit, 16bit, 15bit, and 32bit pixels
Ahh, good. So the Question becomes: - How -
locic points me to 8bit & 16bit : 0 or else 15bit : msb is used 32bit : msb or byte is used
Need to test that. so STORE3 story is ... to be continued.
Tommo Noorduin
Posts 136 29 Apr 2022 09:11
; ammx does not set the status register. ; vector compare ; 8 bytes or 4 words
I hope to contribute a bit by showing some examples.
Thanks a lot for that, an also for the 680x0_instruction_set.ods file which helped me clarify some stuff.
Tommo Noorduin wrote:
Thank you for you post, nice to know you are also looking at the powerfull possibilities the 68080 has.
I hope I can finish my "m68k" tool in the next week or two, and then I can share it with every body. It will give you the possibility of assembling any instructions using the command line, so it would be helpful to encode "touch (a0)" for example. Unfortunately I'm struggling a little bit to find the information needed to make a complete disasm/asm engine. But it's better to have something to start with, than nothing at all. Cheers António
lea pix,a0 load.q #$800001230100ab00,d0 storem3 d0,d0,(a0)+ ; result = 80000123 44444444 storem3 d0,d1,(a0)+ ; result = 80440123 0144ab44 storem3 d0,d2,(a0)+ ; result = 80000123 0100ab00 storem3 d0,d3,(a0)+ ; result = 44440123 01004444 storem3 d0,d4,(a0)+ ; result = 80000123 44444444 illegal
DATA pix REPT 5 dc.l $44444444,$44444444 ENDR
; end code
Notes: VASM needs registers, and the second operand is immediate. so encode storem3 d0,#1,d2 as storem3 d0,d1,d2
(No bug)
A possible mode 2 future upgrade could be: 16bit and test on zero.
Tommo Noorduin
Posts 136 30 Apr 2022 18:59
; average
move.l #$0123fe01,d0 move.l #$0424fd70,d1
pavgb d0,d1,d2 ;result d2 = 0324fe39
; note: ; unsigned rounded up ; pavgw d0,d1,d2 not exist
Tommo Noorduin
Posts 136 01 May 2022 09:39
Note: There is mention of: pabsb, pabsw, touch, pixmrg & tex in connection to ammx.
The first three i can not explane the current behavior. pixmrg might be storem3. tex8/16/24 is not in vasm yet, but i can give the working of it. Just make a request. It has to be in opcodes (dc.w).
.
Okay, One more TRANS, music this time.
With a nice platonic solid, an icosahedron.
With 7 hexagons as segmented lines connecting the pentagons. And every triange it makes filled with more hexagons.