Philippe Flype
(Apollo Team Member)
Posts 299
14 Apr 2016 08:20
| Since the SILVER3 Core, a unique feature is available.
The SAGA Core provides a Clock-Cycle counter Register. It is a new 32-Bits ReadOnly Register that can help developers in some way to optimize their critical routines:
// Register Address
SAGA_CLK_REGISTER = 0xDE0008
The idea of this register is very simple:
Each time you read it, the internal cycles counter is reseted to zero.
// Reset the counter
tst.l SAGA_CLK_REGISTER
// Read the counter
move.l SAGA_CLK_REGISTER,d0
You can use it to determine how many cycles a routine consume, or one single APOLLO instruction.
You can find here an example i made using GCC to illustrate the use of this register:
EXTERNAL LINK
I use GCC 2.95.3 + ADE includes to compile this project.
The tool ouput this result in CLI:
Abcd Dm,Dn : 1
Abcd -(Ax),-(Ay) : 2
Add.l Dm,Dn : 1
Add.l (Ax),Dm : 1
And.l Dm,Dn : 1
And.l (Ax),Dm : 1
Asr.l Dm,Dn : 1
Asr.l #Imm,Dm : 1
Bchg.l Dm,Dn : 1
Bchg.l Dm,(Ax) : 1
Bfextu Dm{Dx:Dy},Dn : 1
Bfextu (Ax){Dx:Dy},Dm : 1
Clr.l Dm : 1
Clr.l (Ax) : 1
Cmp.l Dm,Dn : 1
Cmp.l (Ax),Dm : 1
Divu.l Dm,Dn : 35
Divu.l (Ax),Dm : 35
Divul.l Dm,Dr:Dq : 35
Divul.l (Ax),Dr:Dq : 35
Exg Dm,Dn : 1
Ext.l Dm : 1
Move.l Dm,Dn : 1
Move.l #Imm,Dn : 1
Move.l (Ax),(Ay) : 2
Move.l (Ax)+,(Ay)+ : 2
Move.l -(Ax),-(Ay) : 2
Move.l (Ax,Dm),(Ay,Dn) : 2
Mulu.l Dm,Dn : 2
Mulu.l (Ax),Dm : 2
Neg.l Dm : 1
Neg.l (Ax) : 1
Not.l Dm : 1
Not.l (Ax) : 1
Ror.l Dm,Dn : 1
Ror.l #Imm,Dn : 1
Sub.l Dm,Dn : 1
Sub.l (Ax),Dm : 1
Swap Dn : 1
This output is not exhaustive but yet as you can see and verify by yourself, many instructions takes only 1 cycle.
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Information about the Apollo CPU and FPU.