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No. of Bus Cycles Available to 68080 On OCS/ECS?

Antony Coello

Posts 124
23 Mar 2021 18:06


I didnt get enough room for the full title. It should read:
 
  'Number of bus cycles available to 68080 and DMA devices on a OCS/ECS and Vampire accelerated system?'
 
  Hi all.
 
  Im still evaluating different techniques for game conversion to Amiga/Vampire based boards.
 
  Although Im more used to coding assembly on Atari 68030, I SHOULD be able to catch up if it starts getting technical. (How else would it go with a title like that? lol)
 
  Anyway, from the Vampire as an accelerator and using OCS or ECS, there is bus sharing between CPU and DMA devices, i.e. bus contention for 'chip' RAM.
 
  What would be good to know (if anyone has done this already, to save me the bother) is the number of bus cycles each gets.
 
  A plain A500 and the respective V500v2+ cards as a comparison would be great.
 
  Lastly, I suppose figures for a V4SA would be interesting to see how much improvement has been made. Also, although not really needed by me at the moment, an answer for the respective AGA A1200 and V1200 card would be a handy reference as well, for all code writing owners.
 
  Notes to which core revision used for tests would be useful too! ;)
 
  Oh, and any notes on wait states or anything else I havent thought of is good.


Gunnar von Boehn
(Apollo Team Member)
Posts 5520
23 Mar 2021 18:29


Antony Coello wrote:

'Number of bus cycles available to 68080 and DMA devices on a OCS/ECS and Vampire accelerated system?'

An Amiga with Vampire Accelerator has 2 types of memory.
A) Chip memory
B) Fast memory

The Fast memory is local to the 68080 CPU, and the CPU and RTG Video both use it. The CPU can here do about 500 MB/sec memory access.

The Chip Memory is shared between CPU and Amiga Chipset.
The Chipmemory can maximum do 3.5 MB/sec but if you get this much does depend on how much Planes you have enabled, how many Copper instructions are executed, how many access the Blitter does.
In worst case the chipset can use 100% of the Bus and give the CPU zero cycles. For more detailed information I can recommend you  the Amiga Hardware Reference Manuals.




Antony Coello

Posts 124
23 Mar 2021 20:39


Gunnar von Boehn wrote:

Antony Coello wrote:

  'Number of bus cycles available to 68080 and DMA devices on a OCS/ECS and Vampire accelerated system?'
 

 
  An Amiga with Vampire Accelerator has 2 types of memory.
  A) Chip memory
  B) Fast memory
 
  The Fast memory is local to the 68080 CPU, and the CPU and RTG Video both use it. The CPU can here do about 500 MB/sec memory access.
 
  The Chip Memory is shared between CPU and Amiga Chipset.
  The Chipmemory can maximum do 3.5 MB/sec but if you get this much does depend on how much Planes you have enabled, how many Copper instructions are executed, how many access the Blitter does.
  In worst case the chipset can use 100% of the Bus and give the CPU zero cycles. For more detailed information I can recommend you  the Amiga Hardware Reference Manuals.
 

Ok. I understand bus load is variable depending on DMA devices used. 

Perhaps another way I should word it; is the CPU constrained by the ~7mhz bus speed when using the OCS/ECS display with CHIP RAM and has an unreasonable amount of wait states so it would therefore be far more effective using fast RAM and RTG? (A bit like what would happen if you just put a 100Mhz 68000 in a standard Amiga with no onboard faster RAM, it would just be waiting for its access of the system bus most of the time).

Or is the CPU somehow able to process more cycles when the bus is granted to it? (Im sorry my electronics knowledge is limited, but using some sort of trick like DDR RAM which uses both rise and fall of the cycle for extra acesses or something to the same effect).

Basically Im asking if there are more CPU cycles done in its bus access period than an unaccelerated Amiga and if so, how many on the different cards/V4SA.

Im guessing its more if data read/writes come from the onboard FAST RAM?




Gunnar von Boehn
(Apollo Team Member)
Posts 5520
23 Mar 2021 21:59


Antony Coello wrote:

Perhaps another way I should word it; is the CPU constrained by the ~7mhz bus speed when using the OCS/ECS display with CHIP RAM and has an unreasonable amount of wait states so it would therefore be far more effective using fast RAM and RTG?

 
The Amiga mainboard memory speed is fixed.
No accelerator will change this.
The Amiga mainboard memory will always be 3.5 MB/sec or slower.
For detailed bus cycle diagrams I can recommend you to read the Amiga Hardware reference manual.
 
 
The memory on the Vampire is much faster.
In fact the Vampire is about 150 times faster!
Obviously you want to operate as much as possible inside the Vampire memory and do as little as possible in Amiga mainboard memory.
 
 
One big advantage of the 68080 is that it can talk to 2 memory busses in parallel. Its the only 68K CPU able to do this.
This means it can do a mobo memory acces in parallel to doing fast memory accesses.
 
This will improve performance a lot.

This means from coding perspective you want all your code and data in fast memory.
You can also write to Slow memory in parallel (basically for free) and in parallel to reading  and operating in fast memory.

Writes to slow memory will not take any time and not slow you down, as long you not do more than the bus can take. 
 

On the Vampire-4 the chipmemory is just as fast as the fast memory
So instead slow AMIGA 3.5 MB/sec your have real 500 MB/sec speed there.



Antony Coello

Posts 124
23 Mar 2021 22:48


Thankyou Gunnar. That is exactly the information I wanted to know.
 
  So, FASTRAM/RTG is the way.
 
  I suppose even doing CHIP RAM OCS/ECS stuff is a bit faster then due to parallel R/W on both busses if coded for this situation on the accelerators. (V4SA is best of both worlds).
 
 


Thellier Alain

Posts 126
24 Mar 2021 06:01


I have a similar question: does the vampire SA having DMA cycles sharing as classic Amiga?
I mean does using a big screen résolution "eat" cycles ? So letting less cycles/speed to CPU/blitter/etc ?



Gunnar von Boehn
(Apollo Team Member)
Posts 5520
24 Mar 2021 06:13


thellier alain wrote:

I have a similar question: does the vampire SA having DMA cycles sharing as classic Amiga?
  I mean does using a big screen résolution "eat" cycles ? So letting less cycles/speed to CPU/blitter/etc ?
 

Yes as this is an universial law in live and in physics.
Of course everything in live, in the world and in computer works like this.



Sebastien DA ROCHA

Posts 1
24 Mar 2021 20:17


And are the chip Ram and the Fast Ram in separated buses ?

I mean, if the chipset saturates the chip RAM (high resolution, 3D calculations...) will the 68080 still be table to use the Fast RAM at full speed ?


Gunnar von Boehn
(Apollo Team Member)
Posts 5520
25 Mar 2021 06:38


Sebastien DA ROCHA wrote:

And are the chip Ram and the Fast Ram in separated buses ?
 
I mean, if the chipset saturates the chip RAM (high resolution, 3D calculations...) will the 68080 still be table to use the Fast RAM at full speed ?

When you combine an old Amiga with a Vampire the Chipram and the Fastram are separate busses.
The OCS Amiga resolution of 640pixel in 16 color is enough to saturate the Amiga chipmem. The 68080 can independent of this access its local Fastmemory.

If you use RTG resolutions on the V2 Accelerators than the SAGA display uses Fastmem bandwidth as such truecolor resolution would not be possible with the old Amiga mainboard. This means the memory bandwidth is shared then between SAGA display and CPU.
Please mind that even in most highest display resolution of 1280x720
the CPU is never blocked and still has memory cycles. The memory speed of the Vampire is even in this display much much higher than any other Amiga Accelerator.

So yes if you run SAGA display this will take cycles from the bus the is also used by the CPU.

But you have the mind that the Vampire with 68080 has over 10 times more memory speed than even 68060 CPU accelerators have.
So even with taking cycles from this bus the Vampire will stay faster than other CPU accelerators.

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