DIVSL

DIVSL

/ TDIVS

Operation:
Destination / Source -->; Destination

Assembler Syntax:
DIVSL.L <ea>, Dr:Dq 32/32 -->; 32r:32q

Attributes: Size = (Long)

Description: Divides the signed destination operand by the
signed source operand and stores the signed result in the
destination.

This instruction divides a long word by a long word. The
result is a long-word quotient and a long-word remainder.

Two special condition may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected and set before the inst-
ruction completes. If the instruction detects
an overflow, it sets the overflow condition
code and the operands are unaffected.

Condition Codes:

X Not affected.
N Set if the quotient is negative. Cleared otherwise.
Undefined if overflow or divide by zero occurs.
Z Set if the quotient is zero. Cleared otherwise.
Undefined if overflow or divide by zero occurs.
V Set if the division overflow occurs; undefined if
divide by zero occurs. Cleared otherwise.
C Always cleared.