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Information about the Apollo CPU and FPU.

Understanding the Difference Between CISC and RISC

Gunnar von Boehn
(Apollo Team Member)
Posts 6207
02 Jun 2022 08:36


People often tell me that they know that Motorola 68000 assembly is easy to learn and much easier to code than for example IBM PowerPC assembly.
 
Often I get ask to explain this and to show what advantages the 68000 Assembly has.
 
 
Lets do this today:
 
Lets give some easy to follow examples.
Lets say you program a typical Amiga game like GALAGA.
Lets say after finishing the "bonus level" the player should get a some bonus added to his score.
 
How would you code this on 68K?
ADD.L  #bonuspoints,playerscore
 
Just one instruction is needed to get this done.
And I think its pretty readable: ADD "the bonuspoints" to the "playerscore"
 
Now what would you code on the PowerPC to do exactly the same?

LIS    R2,bonuspoints@h
ADDI    R2,bonuspoints@l
LIS    R3,playerscore@ha
LWZ    R4,playerscore@l(R3)
ADD    R4,R4,R2
STW    R4,playerscore@l(R3)

 
Wow, this is six instructions.
And you will agree they are much harder to read.
 
Six times the instructions means you need to write a lot more code, the code is much harder to read and to debug and the risk of making typos and mistakes is many times higher too.
 
Looking at this simply example makes it very clear why the Amiga with the 68K was such a success. People liked to code on it. And the easy to program CPU is the reason that so many game were developed for Amiga and that the Amiga demo scene was so popular.
 
 
Now lets look at some performance aspects.
ADD.L  #bonuspoints,playerscore
This one instruction needs exactly one CPU cycle on the 68080 CPU.
 

LIS    R2,bonuspoints@h
ADDI    R2,bonuspoints@l
LIS    R3,playerscore@ha
LWZ    R4,playerscore@l(R3)
ADD    R4,R4,R2
STW    R4,playerscore@l(R3)

These six instruction need depending on the PowerPC model 6-7 cycle
You can clearly see the performance disadvantage of a RISC CPU.
 
 
How about memory usage?
The one 68K instruction has a size of 10 byte
The PowerPC instructions have a total size 24 bytes
As you can clearly see the PowerPC code needs a lot more memory.
 
 
As we all know the Amiga 500 did had 512KB Memory which was not so much. And the code of the games needed to be compact to fit in it.
As you will know the majority of games on Amiga were written in assembly and basically all demo coders wrote in assembly of course.
I think its very clear that the good Motorola 68K CPU made this happen.
 
I think having the good 68K CPU was of key influence for the Amiga becoming such a success story.
 
What do you think?


Robo Kupka

Posts 50
02 Jun 2022 14:29


I love 68k CPU architecture and instruction set. Almost perfect orthogonality for ALU and logic functions and incredible variety of addressing modes. FPU instructions are perfect addition to the base i-set. Minimal register usage restrictions. Code is very easy to read.
TELCO companies loved MC68k cpus too, I salvaged many 68020 CPUs from the line and control cards of decommisioned parts. Unfortunately our company did not have any TELCO PBXs based on 68060, but I would be rich now if they had such equipment in operation :)

I would be happy if you, Gunnar, could tell us more about the development of 68080 in FPGA some day, in detail.
- what logical structures your 68080 design is composed of (some blocks diagram)
- how is the DDR3 memory controller designed and attached to CPU ?
- how are the new AMMX instructions designed in the circuit ? Are they part of the ALU, or they are in a separate special block ?
..... I would have too many more questions, I´ll save them for future.

Thanks for reviving Amiga.




Gunnar von Boehn
(Apollo Team Member)
Posts 6207
03 Jun 2022 07:12


Robo Kupka wrote:

I would be happy if you, Gunnar, could tell us more about the development of 68080 in FPGA some day, in detail.
  - what logical structures your 68080 design is composed of (some blocks diagram)

The Apollo 68080 CPU consists of the following units:

1) Icache, able to provide 128 bit of instructions per cycle
2) Learning Branch Prediction Unit
3) Parallel Decoders (able to decode max 4 instruction per cycle)
4) Dependancy checking unit
5) Dual EA unit, able to calc 2 EAs per Cycle
6) DCache Unit, able to in parallel process a read from Dcache,a  Write to DCache, and able to process a parallel Prefetching
7) Hazard unit, solving memory hazards
8) Parallel execution Units, these are Dual Integer ALUs, FPU, AMMX Unit

Cheers
Gunnar


Gunnar von Boehn
(Apollo Team Member)
Posts 6207
07 Jun 2022 09:07


Regarding your question about the Memory Controller:

The memory controller is shared by the CPU and the Amiga DMA channels.
The Super-AGA DMA unit supports 64 DMA channels.
These included DMA for the Bitplanes, the Sprites, the Copper, the Blitter, the Audio channels, the Network Chip, the 3D unit ...

The memory controller support processing several DMA request in flight.


Gilles Dridi

Posts 52
07 Jun 2022 21:29


Dear Gunnar,

Is DMA time slot allocation the same as original Amiga (25 DMA channels) as V4 ?

If not can we called a mix from synchronous and asynchronous DMA ? For audio ?

Gunnar von Boehn wrote:

  Regarding your question about the Memory Controller:
 
  The memory controller is shared by the CPU and the Amiga DMA channels.
  The Super-AGA DMA unit supports 64 DMA channels.
  These included DMA for the Bitplanes, the Sprites, the Copper, the Blitter, the Audio channels, the Network Chip, the 3D unit ...
 
  The memory controller support processing several DMA request in flight.
 

 
  It seems that memory controller was a challenge since Thomas Hirsch NatAmi
  Furthermore Dave Hanie talk in 1992 to replace some synchronous DMA like audio with asynchronous ones ?
  Can you make picture for home schooling futur of DMA time slot allocation / horizontal scan line :
 
  EXTERNAL LINK 
  Keep the faith, breathing and thank for the picture of around and inside Ouf party,
  Regards,
  DGILLES - Arabic console at 18 may 2022 on os4depot.net
 
 

posts 5