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Beyond AMMX

Daniel Sevo

Posts 299
18 Dec 2016 22:36


Stumbled across this PDF called "The significance of SIMD, SSE and
    AVX"
 
  Link:
  EXTERNAL LINK   
   
    In retrospect, what level of SSE would be a meaningful (and realistic) companion for the 68080?
    It doesn't have to be an exact clone, maybe bits and pieces of relevant and useful stuff. Maybe its easier to see a pattern now that we have to luxury of looking back at the evolution of SIMD.
   
    IMO something that handles floats that could accelerate 3d so that something like Wazp3d could be accelerated to a level that competes with hardware Warp3d would be nice and useful.
   
   


Gregthe Canuck

Posts 274
19 Dec 2016 05:21


Hi Daniel -

Good question.

I have every confidence in the Apollo team. The current AMMX instruction set will likely continue to evolve as future needs arise. For example as part of the work on the Riva player a couple of new instructions were added.

Some of the 3D requirements may be satisfied by the new FPU unit. Some may be addressed by AMMX additions. It all comes down to time and priorities.

Cheers!


Daniel Sevo

Posts 299
19 Dec 2016 09:50


If you search old posts you can see Gunnar himself actually mentioned SSE.
Then what we got was MMX along with a good explanation for why it makes sense. It offers good acceleration with relatively little effort and FPGA space.
It makes sense.

But question is, what would be the next step for SIMD that makes sense for this particular architecture.
We already know that this  has lower priority than a number of other things, so Im not holding my breath.
After implementing the already announced stuff Im guessing FPGA space left will be limited.
AFAIK, Intels first SSE version had to deal with similar problems, so they made some clever design compromises. Like merging SIMD-FP mult units with regular FPU etc..

Now.. the first SSE was paired with a 450MHz PIII. So would the same SSE unit be a good pairing for a Pentium 120MHz or does it "mirror" the more advanced architecture of the PIII?

Is there a similar "connection" between current Apollo Core and a useful implementation of SSE or are the limitations purely related to the limits of the chosen FPGA chip?

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