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Apollo Gets "Out of Order" Execution Support.page  1 2 

Gunnar von Boehn
(Apollo Team Member)
Posts 6207
17 Aug 2018 05:45


APOLLO is the world most advanced 68K-Family CPU.
As you know the team continuously improves the APOLLO CPU.
 
The team started now to enable Out Of Order Execution support.
Out of Order Execution is a big step and this change will be done units wise for the core.
Out of Order Execution is a technique used by most modern CPUs to improve performance. The performance benefit does depend on the program. Some algorithms improve significantly with Out of Order support.
Especially for the APOLLO FPU unit which is fully pipelined, the Out of Order support can yield a great performance boosts.
The good news is, the unit which we tested Out of Order successfully already is the FPU.
 
Stay tuned for the next even faster Core release.


Kef Emzy

Posts 50
17 Aug 2018 05:55


Excellent news! I didn't see that one coming... Its almost unreal. Big thanks to you Gunnar and the entire team!


Martin Soerensen

Posts 232
17 Aug 2018 06:08


So does that mean that 68080 will now also use speculative execution? :-)


Gregthe Canuck

Posts 274
17 Aug 2018 06:24



Wow very nice! Another big step forward.

This likely explains the recent quiet period on IRC :)


Vojin Vidanovic
(Needs Verification)
Posts 1916/ 1
17 Aug 2018 06:26


Gunnar von Boehn wrote:

APOLLO is the world most advanced 68K-Family CPU.
  As you know the team continuously improves the APOLLO CPU.

Great news, another "P6 feature" brought in house, soon we will have that "Pentium killer" we always desired of :-)


Peeri the Sunlight

Posts 71
17 Aug 2018 11:19


Fantastic! How much you estimate prefomance boost in normal operation. (Amiga programs what are not optimized for 080)

Small suggestion, could there be random register L|R ($dff...) (readonly, Long word). Now it is quite difficult (and processor time consuming to make good random number generator (trying use cia, v or h beam pos, sp, time etc... ).


Anton Gale

Posts 19
17 Aug 2018 12:18


Great to see the evolution of the 68k and what it could have been.  Thank you for the continued avancements of the APOLLO CPU.


Martin Soerensen

Posts 232
17 Aug 2018 12:22


Peeri the sunlight wrote:
Small suggestion, could there be random register L|R ($dff...) (readonly, Long word). Now it is quite difficult (and processor time consuming to make good random number generator (trying use cia, v or h beam pos, sp, time etc... ).

I doubt that it is any simpler to make a PRNG as a CPU register/instruction as compared to plain software, unless it is possible to implement a Geiger-counter in an FPGA? :-)


Peeri the Sunlight

Posts 71
17 Aug 2018 12:38


Martin Soerensen wrote:

  I doubt that it is any simpler to make a PRNG as a CPU register/instruction as compared to plain software, unless it is possible to implement a Geiger-counter in an FPGA? :-)

I think so too.. But BigGun is so genius that he might do something clerver... :D


Andrew Copland

Posts 113
17 Aug 2018 14:11


Don't try to come up with a good PRNG yourself, just use a known good one and precalculate a bunch of values using it ;)


Andrew Copland

Posts 113
17 Aug 2018 14:12


Cool news Gunnar.

Since you mention the FPU I'm presuming this is future work that will appear in the Gold 3 core?


Martin Soerensen

Posts 232
17 Aug 2018 14:44


Andrew Copland wrote:
Since you mention the FPU I'm presuming this is future work that will appear in the Gold 3 core?

Or in a 2.x core. The FPU is already enabled and working in current cores.


Andrew Copland

Posts 113
17 Aug 2018 15:22


Martin Soerensen wrote:

  Or in a 2.x core. The FPU is already enabled and working in current cores.

My assumption was that since the FPU is already slightly cut down (I think?) in the 2.x cores for existing Vampire boards due to FPGA space restrictions, and since OoO execution will require things like a rolling outgoing instruction window plus other additional hardware to handle the reordering that it will take more resources than are available.

However I didn't actually mean to say Gold 3, I meant to write V4 :)


Gunnar von Boehn
(Apollo Team Member)
Posts 6207
17 Aug 2018 19:28


Martin Soerensen wrote:

So does that mean that 68080 will now also use speculative execution? :-)

Yes, 68080 does already support speculative execution.



Gunnar von Boehn
(Apollo Team Member)
Posts 6207
17 Aug 2018 19:31


Andrew Copland wrote:

since OoO execution will require things like a rolling outgoing instruction window plus other additional hardware to handle the reordering that it will take more resources than are available.

Actually the APOLLO FPU has from the beginning designed with all resources which you need to use OoO.
The Apollo FPU supported from beginning Pipelining and parallel execution of over 10 FPU instructions at the same time.
The resources that you need to enable and track can basically for free also support OoO.

This means GOLD 2.11 can enable FPU OoO for no extra FPGA cost.



Vojin Vidanovic
(Needs Verification)
Posts 1916/ 1
17 Aug 2018 21:14


Andrew Copland wrote:

  My assumption was that since the FPU is already slightly cut down (I think?) in the 2.x cores for existing Vampire boards due to FPGA space restrictions, and since OoO execution will require things like a rolling outgoing instruction window plus other additional hardware to handle the reordering that it will take more resources than are available.

We will see how team will handle v2 support in future, but there is a physical limit to FPGA LE space.It might be various cores with options (just AGA+full CPU, full FPU no AGA etc.) or at some rounded point like GOLD3.x it might become impossible to add new feats, but to bugfix previous.

But based on how much was done in v2 era, one must expect v4 as "days of glory" with now full FPU, larger caches, higher frequency and OO :-)

Well, "FPU was cut down". No, when compared to 882, yes when compared to full 80-bit+ fully piplined Apollo FPU, we expect to see with V4.



John Heritage

Posts 111
17 Aug 2018 23:08


That's a huge complexity increase -- quite an achievement for Apollo Team!  This should allow a consistent and truly substantial improvement in ILP over 68060.

Is the OOO engine enabled for the entirity of the 4-wide Integer core?  (I believe 68080 was said to be able to execute up to 4 instructions at once).  Any influence on maximum clock speed?  Power consumption?


Daniel Sevo

Posts 299
17 Aug 2018 23:25


This is pretty cool stuff. Just when you think performance has peaked.. However.. it also made me wonder if there is a "final specification" for the Apollo Core? At least for the current generation of FPGAs?
Will there be a day when Big Gun will be able to say, "this is the perfect AC68080", now lets do a 68090 ;-)

I guess you can have the "perfect" instruction set (in this 68k architecture context)  etc.. but still find room for optimizations in the memory controller or extending AMMX further. I guess AMMX extensions could be expanded "forever" to include more 3dnow! like instructions for 3d stuff or somnething similar (developed alongside a custom version of Wazp3d that utilizes this power.).

Anyway, its a fascinating project to follow however you look at it, but curiosity makes me ask if a "final spec" exists or is this something that will continue to evolve and once one particular FPGA model is too limiting simply take the leap to the next FPGA and so on...




Andrew Miller

Posts 352
17 Aug 2018 23:42


Im thinking there will be a kind of final spec with the v4 model. Where they may go asic at the end of it.
Im wondering if theyll do an asic with the full core with saga or have them as different asics, one for cpu and one for saga chipset.

Either way its an interesting time to have an amiga, imagine a 1-2ghz asic running assembly written code on an amiga vs the massive code bloat from all other operating systems xD using things like java etc


Renee Cousins
(Apollo Team Member)
Posts 142
18 Aug 2018 01:51


Gunnar von Boehn wrote:
  The team started now to enable Out Of Order Execution support.

YAAAAAAAAAAAS!!!!

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