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Information about the Apollo CPU and FPU.

Comparing 68060 FPU and 68080 FPUpage  1 2 

Chris Dennett

Posts 58
18 Jan 2018 16:07


There is probably some easy fruit to pick out there


Mallagan Bellator

Posts 259
21 Jan 2018 02:06


Vojin Vidanovic wrote:

Peter Heginbotham wrote:

  For me, the effort should be spent in updating the various compilers and programming tools to generate optimized code for the new FPU functionality. Maybe some community funded bounty?
 

 
  Dont forget some CPU related "NOT hand by hand assembly finetuning" for 080 overall. Generally tools that would optimize existing 68k code for 080/MMX/2.7 mixed FPU/v4 full FPU would be most benefitial.

It would probably be quite hard to write a compiler that generates perfect and always optimised code at all times, and for all usage, putting the lines in the best possible order, removing functions that are not needed for the code to run with the best performance, and so on.

This said, I do think somebody should start working on it and see what they can do. You always gotta start somewhere, and then see how far you’ll get, and how fast you can make things run


Will 'Akiko' G.

Posts 9
29 Jan 2018 17:58


Gunnar von Boehn wrote:

  68060 FPU
  FDIV instruction needs 35 Clock cycles.

Do you mind if I throw in my knowlegde about the 060 micro-architecture?

It is 37 to 39 cycles depending on the addressing mode for the computation alone. The read stage can take 0 or 1 cycle and the write stage is always done in 0 cycles. Calculation is always done in extended precision (80 bit) and that is the reason fdiv, fsdiv, fddiv and fsgldiv have exactly the same cycle amounts.


Samuel Devulder

Posts 111
02 Feb 2018 20:39


Mallagan Bellator wrote:

  It would be totally sweet if someone optimized Quake to utilize this!
 

I do! See the "Quake" thread ( CLICK HERE ) for a more detailed answer.

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