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Apollo Team Activity Report (February 2018)

Renaud Schweingruber

Posts 148
25 Feb 2018 17:51


Apollo Team Activity Report (February 2018)

It’s been a while (since December actually) that an activity report wasn’t posted. I fear we were all too busy eating turkey and trying to find a cure for new year hangover to make it. Another explanation could also be we are just lazy. Anyway, here is it again !

GOLD2.7 – Last steps before release
GOLD2.5 was released officially on July 2017 but was a small update for GOLD2 which has released in January 2017. Technically, GOLD2.7 took nearly a year to get to its final steps. That could look long but… hey… let’s put things into some perspective : Apollo Team developed a complete FPU in one year. How long did it took to engineer teams at Motorola to do so? The 68881 was introduced in 1984, 5 years after release of the 68000.

But while I’m telling that, I can hear the voice of the crowd in background: “we don’t give a f*** about your f***** story, when are you gonna finally release it ???? you’ve been teasing it for months !!!”

Okay. “Not far” (to not mention the well known “two more weeks” words) would be the best answer but it would not help us if we do not want our houses to be set on fire within next minutes.

GOLD2.7 entered now a “freeze” period, in which new functionalities will not be added and major changes to code avoided. Apollo Team is hunting last remaining bugs and testing it intensively before the release.

To squeeze our nice FPU into the Vampire V2 FPGA remaining space while still maintaining a stable core, a complete rewrite of some important parts of the core were needed during last weeks. This rewrite was super tricky and went from complete dead beta cores to actual super FPU cores.

GOLD2 core is revision 3686, current GOLD2.7 core is today in the 49xx range. Getting it up there required more than 1300 compilations of the core since a year, for both V600 and V500, hence a total of more than 2600 compilations.

GOLD2.7 FPU – More details
68080 FPU is unlike some emulators or next gen OS a complete 80-bit FPU. For Vampire V2 GOLD2.7 release, its precision has been reduced to be able to fit it into the FPGA remaining space. GOLD2.7 68080 FPU is fast and good enough to run most FPU applications, games and demos at a descent speed while offering an acceptable floating-point precision.

Our magician flype wrote a great technical datasheet to explain in details our FPU. I highly advice you to take some minutes to read it.

EXTERNAL LINK 

GOLD2.7 – Registration process
The registration process while being available for months has not collected all the required serial numbers we hoped. We took the decision for GOLD2.7 to merge all our available registered serial numbers with serials provided by majsta’s so people who had not enough time to register their board will not have to suffer our security system.

Core will have a whitelist included. This whitelist will be updated on a regular basis depending on registration list growth.

GOLD2.7 – Technical warning – Read it!
GOLD2.7 core update WILL put pressure on your Vampire FPGA. We have seen some FPGA that were too weak to support GOLD2.7 while being super stable on GOLD2 and GOLD2.5.

While in the past we *recommended* to get an USB Blaster, we now say that having an USB Blaster nearby is *mandatory*.

If your FPGA is too weak to support GOLD2.7 core, we can offer an easy technical fix, which requires very basic soldering skills (I was able to make it, you should too, really) and two 220uF/10V radial electrolytic capacitors. Just get in touch with us if this happens and we will guide you through the process.

EXTERNAL LINK 

Vampire V4 – Was aiming at Q4’17? Meh.
We are late, yes.

We have been quite optimistic regarding our objective to release if before of the end year, yes.

Will it be awesome? Yes.

Despite being late and covered by the great answer “it’s normal in Amigaland”, Apollo Team is still working hard to get Vampire V4 on the market as soon as possible. Ceaich, BigGun and Claude have been hunting bugs for weeks and we hope to go forward soon with it.

Vampire 600 V2
A new batch of Vampire 600 V2 is on the way to majsta’s hideout to fullfil pending and new orders of that great card. Majsta took the opportunity to add various fix to and improve the global design.

Final words
I would really like to bring better news regarding release dates or so but we can’t compare our hobbyist project as big releases ala Microsoft or Apple, nobody should expect such commitment from us as we don’t have needed resources for. Some patience is still required, development of such complex products is not straightforward and we often have to suffer big regressions before getting awaited improvements.

GOLD2.7 will be a big milestone for Apollo Team, meaning that after its release, we can focus on next innovations (who mentioned GOLD3?).

Apollo Team never surrenders, Apollo Team does deliver :)


Michael Borrmann

Posts 24
26 Feb 2018 06:06


Super nice... :)

Looking forward to the V4, and it's great that you managed to get the FPU into the existing core...


Martin Soerensen

Posts 182
26 Feb 2018 10:04


Thanks for the update. I knew that you were working hard on finishing Gold 2.7, but I didn't expect that you would be able to implement a fast and compatible FPU in such a short time. If I ever used a hat, I'd take it off for you all. I guess my bicycle helmet will have to do. :-)

I will certainly be looking forward to trying out the final release on both my 500 and 600 and hopefully be able to watch those RTG+FPU 060 demos that were not running or too slow with the old femu.

Regarding the fix you mention, would it make sense to apply it to my Vampires no matter if it seems to handle G2.7 fine without it? I guess it is extra supply decoupling and as such, adding it should never make it worse.


Peter Heginbotham

Posts 121
26 Feb 2018 11:22


Hi

The furture looks good, couple of points

For the techincal fix can the Wiki be updated to include the detail on the capacitors and location etc

Can you send a these "Apollo Team Activity Report" to the registered users as it would flush and email address issues before the release of the next core.


Aksel Andersen

Posts 108
26 Feb 2018 15:33


Does this fix apply for both v500 and v600?

Cheers


Tango One

Posts 83
26 Feb 2018 17:12


Is there any more news on v1200. ?




Mr-Z EdgeOfPanic

Posts 155
26 Feb 2018 18:09


Michael Borrmann wrote:

Super nice... :)
 
  Looking forward to the V4, and it's great that you managed to get the FPU into the existing core...

It did require some shoehorns to squeeze it in the C3 :)



Mr-Z EdgeOfPanic

Posts 155
26 Feb 2018 18:13


Warning: Be sure cap polarity is correct!
Warning: add the caps do not remove original ones
Warning: Be carefull with isolation material, do not use playdough!
I set my caps upright on the V600 with no isolation material.
     
Powermod on V600: EXTERNAL LINK       
V500+ will not need it.

top tip: if you don't have any experience or feel uncertain about doing it, please consult a professional.
     
     
         


Istvan Hegedus

Posts 4
26 Feb 2018 19:56


If the C3 FPGA is now nearly fully utilized does it mean there will be no space in it for GOLD3 and AGA?



Roy Gillotti

Posts 153
26 Feb 2018 20:06


Edit: dumb comment, wrote before properly reading, please delete.


Sean Sk

Posts 106
27 Feb 2018 05:01


Mr-Z EdgeOfPanic wrote:

  Warning: Be carefull with isolation material, do not use playdough!     
 

 
  Insulation material would only be necessary if you use polymer capacitors as shown in that video.
  If you use normal electrolytic capacitors the capacitor body is generally insulated anyway therefore not requiring the use of any other material, which I think looks messy.


Alan Haynes

Posts 85
27 Feb 2018 06:13


Excellent work Apollo Team. Move to the head of the class.

All of this does beg the question though.
Was space reserved in the core for the AGA chipset or will we need the V4 to get those features?


Leigh Russ

Posts 76
28 Feb 2018 16:00


A valid point was raised over on Facebook. Is having all the serial numbers stored in a whitelist within the core itself not taking up valuable space, which is already limited as it is?


Henryk Richter

Posts 68
28 Feb 2018 16:13


Leigh Russ wrote:

  A valid point was raised over on Facebook. Is having all the serial numbers stored in a whitelist within the core itself not taking up valuable space, which is already limited as it is?
 

  Please accept that Facebook is not a credible source of information, especially when it comes to the activity of the Apollo team.
 
  The list of serials is not something that takes up precious logic units in the FPGA itself. There are other ways of storing the respective information. FWIW: serial number tracking was actually implemented when all other functionality for Gold 2.7 was finished already.

posts 14