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"This CPU that's on the Vampire is the best CPU I've ever had in an Amiga"

- Stephen Jones,
Director and Developer





Overview


Back in the 80s, Motorola was leading the market with its 680x0 CISC processors range and selling it to big companies like HP, Apple, Atari, Commodore, NeXT, SEGA and others.

Today, the 680x0 is still used by industrial machines, the aircraft industry, cars vendors and fans of retro-computing around the world.

But what if we could have even more powerful 68k processor today? We would like to introduce you Apollo Core 68080!


Apollo Core 68080 is the latest, natural and modern evolution of 68k processors


A new CPU that is code-compatible with all previous Motorola 68k processors

Correcting the bugs found in earlier 68k designs

And adds most of the cool features invented since production of the 68k line of processors stopped



Advantages


  • Fast, available, affordable, compatible

  • Fully pipelined

  • Superscalar

  • Hyper-threaded

  • Executes up to 4 instructions per clock cycle

  • Two address calculation engines

  • Two integer execution engines

  • Market-leading code density

  • Optimal cache utilization

  • Separate data and instruction caches, supporting concurrent fetch/read/write per clock cycle

  • Automatic memory pre-fetching

  • Memory stream detection

  • Store buffer

  • Branch prediction

  • Fully pipelined, double/extended FPU

  • Dual Bus Architecture


Glossary:

Hyper-threaded design allows a single processor or processor core to handle two independent sets of instructions at the same time. A hyper-threaded processor can fill otherwise-idle time with a second process for each core, improving multitasking and performance of multithreading single applications.

Branch prediction is a feature formerly found only in high-end mainframe processors. It enables the processor to keep the instruction pipeline full while running at a high rate of speed.

Superscalar architecture was initially associated with high-output reduced instruction set computer (RISC) chips. A RISC chip has a less complicated instruction set with fewer and simpler instructions. Although each instruction accomplishes less, the overall clock speed can be higher, which usually increases performance.

Dual Buss Architecture enables the cache of the newer processors to run at full speed inside the processor core on an independent bus, leaving the main CPU bus to handle normal data flowing in and out of the chip.



68080 is designed in a modern way


Apollo Core 68080 has many modern features which only latest processors have.

68080 CPU, when embedded on FPGA chips such as Cyclone III and Cyclone V, is much faster than the fastest 68060. This is possible because of the advanced design of the Apollo Core, large and fast instruction/data caches, and very fast read/write memory access.

While the clock-rate of the 68080 is currently limited by the FPGA chip - the performance of the CPU is extremely high for its clock.


68080 has much higher performance than a 800 MHz 68030 in nearly all cases|


The performance of the Apollo CPU ranges between Pentium 100 to the Pentium 3 @1000 MHz - depending on which enhancements and features you use within your program.

68080 is clearly the fastest 68K ever - and even outruns PowerPC machines at 1000MHz in some benchmarks.



68080 improves 68k family


68060 ICache provides a maximum of 32 bits per cycle. As 68k instructions have a size of 16 bits or more, 32 bits allows for 2 of the shortest 68k instructions to execute.

The 68060 is often limited by this, as many 68k instructions are 32 bits, 48 bits or longer. Motorola was aware of this bottleneck and the 68060-dev-team wanted actually to double the ICache fetch... but this never happened.



Advantage over PPC and ARM

By design, a RISC processor has a an advantage due to "operations per instruction".

For the hardware developer, the RISC makes it easier to pipeline. This means you need less knowledge as hardware designer to fully pipeline a RISC ISA. As the 68020 was not fully pipelined, it has a disadvantage.


The 68080 is 100% pipelined and easily beats the ARM  |


A CISC ISA requires more "thinking" for the hardware engineer. We did this "thinking" for the 68080.

RISC ISA makes is "easier" for the hardware manufacturers to produce a CPU. We did not follow the easy way.

You can compare a RISC CPU with a bicycle - and a CISC CPU with a motorbike. Yes, it's much easier and cheaper to produce a bicycle. True, the very first motorcycle was maybe even slower than a bicycle. But today motorbikes are a lot more powerful and much faster than bicyles.

There was a time in the '80's when the hardware companies did not know how to optimally pipeline CISC designs. By the early '90's, the RISC was a "cheat" which allowed companies to easily pipeline their cores - and this gave RISC an edge, but only for a few years.

Since the biggest CPU manufacturers have learned how to optimally pipeline the CISC architecture, CISC is leading again. This is true of the 68080 as well.

The performance of the Apollo CPU can range from a Pentium 100 to a Pentium 3 @1000 MHz, depending on which enhancements and features you use within your program.

68080 is clearly the fastest 68K ever - and even outperforms PowerPC machines at 1000MHz for some benchmarks.






AMMX


AMMX is a 64 Bit SIMD extension to the 68k processor.

It shares the 64 Bit width with popular MMX implementation, and is more geared towards the SIMD extensions in RISC architectures (AltiVEC, Wireless MMX).

Thanks to AMXX, games on Vampires run much faster that on other accelerators or Amiga computers.

For more information please check dedicated AMMX page.



68080 and Amiga mainboards


Apollo Core has TWO busses which can operate completely in parallel at the same time.

This makes the 68080 unique - as the original 68k CPUs have only a single buss.


Apollo Core is also multilingual. Its buss recognizes the protocols used by the 68000/68010/68020/68030/68040/68060.

This enables the 68080 to run all Amiga mainboards from Amiga 1000 to Amiga 4000.


The second buss of the Apollo Core supports SDRAM and DDRAM

This means it can use all modern memory chips on the market - which any other 68K cannot do.

The buss design is one of the reasons Apollo Core is able to deliver high performance.


68080 in FPGA


Apollo Core surpases the performance of 68060 ASIC by far - utilizing a low cost FPGA.

While there are other FPGA 68K clones, Apollo Core 68080 is the only one designed like a modern processor that allows it to deliver great performance.

Because of this design difference from ground up, only the 68080 can be used to make the fastest accelerators for Amiga..

It is designed according to modern CPU standards, is fully written in VHDL, and is intended to run on Altera Cyclone FPGAs.

Utilizing an FPGA, the Apollo Core offers a good combination of moderate FPGA space consumption and excellent performance.



68080 product range


Currently the Apollo Core is featured in four products designed for Amiga users. That includes three processor accelerators for Amiga machines listed below:

Apollo Accelerators series:


Apart from that, the 68080 is featured in a new AMIGA-compatible computer:



68080 assembler code samples


Please check out our Apollo Wiki page for ASM code samples. Here, you can find various examples to help assembly language (ASM) beginners to get started with developing on the Apollo Core 68080 CPU.

If you have questions or want help with ASM, please visit our dedicated Forum section or the Discord #ApolloTeam server.



Features


Apollo Core is not only the fastest 680x0 series CPU ever, it also is the most fully featured:

Feature 68000 68020 68030 68040 68060 68080
68 ISA + + + + + +
Extended EA-modes - + + + + +
BITFIELDS - + + + + +
64Bit MUL - + + + - +
64Bit DIV - + + + - +
Inst Cache - + + + + +
Data Cache - - + + + +
Fully pipelined - - - + + +
Super Scalar - - - - + +
Store Buffer - - - - + +
Static Branch Prediction - - - + + +
Dynamic Branch Prediction - - - - + +
Branch Target Cache - - - - + +
Conditional Rewrite - - - - - +
Linkstack - - - - - +
Instruction Fusing - - - - - +
Instruction Bonding - - - - - +
64-Bit Support - - - - - +
3-opp instructions - - - - - +
Memory-Prefetch - - - - - +
Multimedia Extension - - - - - +
3D Instructions - - - - - +
Selfmodify Support + - - - - +
Integrated FPU - - - + + +
Pipelined FPU - - - - - +
Out of Order FPU - - - - - +
Out of Order CPU - - - - - +
Peak Inst/Cycle 0.25 0.5 0.5 1 2 4

Plus / green color means feature is present
Minus / grey color means feature is not available



Addressing Modes


Very fast EA-modes
free, up to many per Cycle
Fast EA-modes
free, up to 1 per Cycle
Slow EA-modes
these EA take 4 Cycle
Dn
(An)
([dis, An, Xn*Scale], dis)
An
(An)+
([dis, An], Xn*Scale, dis)
#
-(An)
(d16, An)
(d8, An, Xn*Scale)
(bd, An, Xn*Scale)
(d16, PC)
(d8, PC, Xn*Scale)
(bd, PC, Xn*Scale)
(xxx).W
(xxx).L


 

Instructions


ADDA
ADDQ
SUBA
SUBQ
CMPA
LEA
PEA
MOVEA


ABCD
SBCD
NBCD
PACK
UNPK


TAS
CAS
CAS2

RTE
MOVES
MOVEC
RESET
STOP

ADD
ADDI
ADDQ
ADDX
SUB
SUBI
SUBQ
SUBX
TST
CMP
CMP2
CMPI
CMPM
NEG
NEGX
MULU
MULS
DIVU
DIVUL
DIVS
DIVSL
EXT
EXTB

BTST
BSET
BCHG
BCLR
BFTST
BFCHG
BFSET
BFCLR
BFEXTU
BFEXTS
BFINS
BFFFO
AND
ANDI
ANDN
OR
ORI
EOR
EORI
NOT


ASR
ASL
LSR
LSL
ROR
ROL
ROXR
ROXL
Scc
DBRA
BCC
BRA
BSR
JMP
JSR
RTS
RTD
RTR
LINK
UNLK


CHK
CHK2
TRAP
TRAPV
TRAPcc
EXG
SWAP
CLR
MOVEQ
MOVE
MOVEM
MOVE16
MOVEP
MOVEX
PERM

NOP
ILLEGAL


ANDI to CCR
ORI to CCR
EORI to CCR
MOVE to CCR
MOVE from CCR
MOVE from SR
MOVE to USP
MOVE from USP
FRESTORE
FSAVE
FMOVE
FADD
FSUB
FABS
FNEG
FMUL
FDIV

BSEL
PPERM
PAVGU
PSUB
PSUBUS
PADD
PADDUS




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