APOLLO CPU CORE Product Brief
The APOLLO Core offers a superscalar integer performance
of over 300 MIPS at 200 MHz.
Leveraging many of the same performance enhancements used by RISC designs as well as providing innovative architectural techniques, the APOLLO harnesses new levels of performance. The APOLLO Core employs a deep pipeline, dual issue superscalar execution, a branch cache, sixteen Kbytes each of on-chip instruction and data caches. The APOLLO allows simultaneous execution of two integer instructions (or an integer and a floating-point instruction) and one branch instruction during each clock.
The APOLLO features a full internal Harvard architecture. The instruction and data caches are designed to support concurrent instruction fetch, operand read, and operand write references on every clock.
The operand data cache permits simultaneous read and write access each clock.
The APOLLO variable-length instruction system provides market leading code density. The variable-length instruction are internally decoded and dispatched to four pipelined RISC operand execution engines where they are then executed.
The branch cache also plays a major role in achieving the high performance levels of the APOLLO. It has been implemented such that most branches are executed in zero cycles. Using a technique known as branch folding, the branch cache allows the instruction fetch pipeline to detect and change the instruction prefetch
stream before the change of flow affects the instruction execution engines, minimizing the need for pipeline refill.
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